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74VHC273 Octal D-Type Flip-Flop
April 1994 Revised April 1999
74VHC273 Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal Dtype flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The register has a common buffered Clock (CP) which is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX= 165 MHz (typ) at VCC = 5V s Low power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Low noise: VOLP = 0.9V (max) s Pin and function compatible with 74HC273
Ordering Code:
Order Number 74VHC273M 74VHC273SJ 74VHC273MTC 74VHC273N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D7 MR CP Q0-Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011670.prf
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74VHC273
Function Table
Operating Mode MR Reset (Clear) Load '1' Load '0'
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition
Inputs CP Dn X H L
Outputs Qn L H L
L H H

X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC273
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 75 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 ns/V 100 ns/V 0 ns/V 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 5.5 4.0 40.0 0 - 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 V A A IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND V V IOH = -4 mA IOH = -8 mA VIN = VIH IOL = 50 A or VIL V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = VIH IOH = -50 A or VIL Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3)
Note 3: Parameter guaranteed by design.
Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage
VCC (V) 5.0 5.0 5.0 5.0
TA = 25C Typ 0.6 -0.6 Limits 0.9 -0.9 3.5 1.5
Units V V V V
Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
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74VHC273
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency 5.0 0.5 tPLH tPHL Propagation Delay Time (CK - Q) 5.0 0.5 tPHL Propagation Delay Time (MR - Q) 5.0 0.5 tOSLH tOSHL CIN CPD Output to Output Skew Input Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design tOSLH = |tPLHmax - tPLHmin|; tOSHL = |tPHLmax - tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pieces of the Flip Flop operates can be calculated by the equation: CPD (total) = 22 + 9n.
VCC (V) 3.3 0.3
TA = 25C Min 75 50 120 80 Typ 120 75 165 110 8.7 11.2 5.8 7.3 8.9 11.4 5.2 6.7 13.6 17.1 9.0 11.0 13.6 17.1 8.5 10.5 1.5 1.0 4 31 10 Max
TA = -40C to +85C Min 65 45 100 70 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 16.0 19.5 10.5 12.5 16.0 19.5 10.0 12.0 1.5 1.0 10 Max
Units MHz MHz ns ns ns ns ns pF pF
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF (Note 4) VCC = Open (Note 5) CL = 50 pF CL = 50 pF
3.3 0.3
3.3 0.3
3.3 0.3 5.0 0.5
AC Operating Requirements
Symbol tW(L) tW(H) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Parameter Minimum Pulse Width (CK) VCC (V) (Note 6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Minimum Removal Time (MR) 3.3 5.0
Note 6: VCC is 3.3 0.3V or 5.0 0.5V
TA = 25C Typ
TA = -40C to +85C Guaranteed Minimum 5.5 5.0 5.0 5.0 5.5 4.5 1.0 1.0 2.5 2.0 6.5 5.0 6.0 ns 5.0 6.5 4.5 1.0 1.0 2.5 2.0 ns ns ns Units
ns
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74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74VHC273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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